# Acute North America — Full LLM-Readable Corpus
# https://acutena.com/llms-full.txt

> Concatenated Learn articles, product family summaries, and protocol
> summaries for AI crawlers and answer engines. English source content.
> Canonical short index: https://acutena.com/llms.txt

## Product Families

### TravelBus Series
URL: https://acutena.com/en/products/travelbus/
19–25 Channel Protocol & Logic Analyzers — 800 MHz Timing, 200 MHz State Analysis, 120+ Decoders
Entry-level USB 3.0 protocol and logic analyzers with 19–25 channels. Ideal for embedded protocol debug with I2C, SPI, UART, CAN, and more. The TB3016B adds differential signal support.

### TravelLogic Series
URL: https://acutena.com/en/products/travellogic/
34-Channel Logic Analyzers — 2 GHz Timing, 200 MHz State Analysis, Up to 8 Gb Memory
Professional 34-channel USB 3.0 logic analyzers with up to 2 GHz timing analysis and 200 MHz state analysis. The TL4000 family delivers deep memory, 120+ protocol decoders, and cascading support.

### LA4000 Series
URL: https://acutena.com/en/products/la4000/
68–136 Channel Logic Analyzers — 4 GHz Timing, 400 MHz State, 32 Gb Memory, Cascadable
High-performance 68–136 channel logic analyzers with 4 GHz timing, 400 MHz state analysis, and 32 Gb memory. Supports multi-unit cascading and optional LVDS differential input.

### MSO2000 Series
URL: https://acutena.com/en/products/mso2000/
2-Channel Oscilloscope + 8–16 Channel Logic Analyzer — 2 GHz Timing, Up to 8 Gb Memory
Mixed-signal oscilloscopes combining 2-channel DSO with 8–16 channel logic analyzer in one USB 3.0 instrument. Built-in protocol decode and analysis for combined analog/digital debug.

### TravelScope Series
URL: https://acutena.com/en/products/travelscope/
4-Channel Digital Oscilloscopes — 200 MHz Bandwidth, 1 GS/s, 128 Mpts Memory
4-channel USB 3.0 PC-based digital storage oscilloscopes with up to 200 MHz bandwidth, 1 GS/s sample rate, and deep memory. Includes Data Logger for long-duration recording.

### MSO3000 Series
URL: https://acutena.com/en/products/mso3000/
4-Channel Oscilloscope + 16-Channel Logic Analyzer — 200 MHz Bandwidth, 1 GS/s, 120+ Protocol Decoders
Advanced mixed-signal oscilloscopes combining 4-channel DSO with 16-channel logic analyzer. Up to 200 MHz bandwidth, 1 GS/s sample rate, and comprehensive protocol decode — the most capable combined instrument.

### BusFinder Series
URL: https://acutena.com/en/products/busfinder/
Dedicated protocol analyzers for eMMC, SD, MIPI
Dedicated protocol analyzer hardware for deep bus-level analysis. Supports eMMC, SD, MIPI D-PHY, and other high-speed interfaces with real-time decode, command statistics, and packet logging.

### TravelData Series
URL: https://acutena.com/en/products/traveldata/
8–16 Channel Digital Pattern Generators — 200 Mbps, Up to 256 Mb Pattern Depth
Compact USB 3.0 digital pattern generators with 8–16 output channels for stimulus generation, protocol simulation, and automated test signal creation.

### DG4000 Series
URL: https://acutena.com/en/products/digital-pattern-generators/
64–128ch pattern generators — DG4000 series
High-channel-count digital pattern generators with 64–128 output channels for complex stimulus generation. Ideal for ASIC/FPGA validation and production test.

### PX2000 Series
URL: https://acutena.com/en/products/protocol-exerciser/
Protocol exerciser for bus testing & compliance
The PX2816B Protocol Exerciser enables active bus exercising and compliance testing for I2C, SPI, UART, and other serial protocols. Generate protocol traffic, simulate devices, and validate bus behavior — a companion to the BusFinder protocol analyzer.

### Differential Probes
URL: https://acutena.com/en/products/differential-probes/
25 MHz & 100 MHz differential probes
High-voltage differential probes in 25 MHz and 100 MHz bandwidth models. Safe measurement of floating and differential signals up to 1400V with high CMRR.

## Protocols

### I2C — Inter-Integrated Circuit
URL: https://acutena.com/en/protocols/i2c/
Category: embedded
I2C (Inter-Integrated Circuit) is a synchronous, multi-master, multi-slave serial communication bus invented by Philips Semiconductor. It uses just two signal lines — SDA (Serial Data) and SCL (Serial Clock) — to connect multiple integrated circuits on a single board. I2C is one of the most widely used protocols in embedded systems, found in sensors, EEPROMs, real-time clocks, display controllers, power management ICs, and countless other peripherals. The protocol supports multiple devices on the same bus using 7-bit or 10-bit addressing, with standard data rates of 100 kHz, 400 kHz (Fast Mode…

### SPI — Serial Peripheral Interface
URL: https://acutena.com/en/protocols/spi/
Category: embedded
SPI (Serial Peripheral Interface) is a synchronous serial communication protocol widely used for high-speed, short-distance communication between microcontrollers and peripheral devices. Developed by Motorola, SPI uses a master-slave architecture with four primary signals: SCLK (Serial Clock), MOSI (Master Out Slave In), MISO (Master In Slave Out), and CS/SS (Chip Select/Slave Select). Unlike I2C, SPI operates in full-duplex mode, allowing simultaneous data transmission and reception. SPI is the preferred interface for NOR flash memory, SD cards, display controllers, ADCs, DACs, and high-speed…

### CAN FD — Controller Area Network Flexible Data-Rate
URL: https://acutena.com/en/protocols/can-fd/
Category: automotive
CAN FD (Controller Area Network with Flexible Data-Rate) is an extension of the classic CAN protocol, developed by Bosch to address the growing bandwidth demands of modern automotive and industrial networks. CAN FD maintains backward compatibility with CAN 2.0 while introducing two key improvements: larger data payloads (up to 64 bytes per frame, compared to 8 bytes in classic CAN) and faster data-phase bit rates (up to 8 Mbps or higher, while the arbitration phase remains at up to 1 Mbps). The protocol uses a single differential pair (CAN H and CAN L) and retains CAN's robust error detection…

### UART — Universal Asynchronous Receiver-Transmitter
URL: https://acutena.com/en/protocols/uart/
Category: embedded
UART (Universal Asynchronous Receiver-Transmitter) is one of the oldest and most widely used serial communication interfaces in electronics. Unlike synchronous protocols such as SPI and I2C, UART does not use a shared clock signal — instead, both the transmitter and receiver must agree on a baud rate (common rates include 9600, 115200, 460800, and up to several Mbps). UART communication uses two data lines: TX (Transmit) and RX (Receive), enabling full-duplex bidirectional communication. Each data frame consists of a start bit, 5 to 9 data bits, an optional parity bit, and one or two stop bits…

### USB PD — USB Power Delivery
URL: https://acutena.com/en/protocols/usb-pd/
Category: power
USB Power Delivery (USB PD) is a protocol specification that enables flexible power negotiation over USB Type-C connections, supporting power levels up to 240W (48V at 5A) under the Extended Power Range specification. USB PD communication occurs over the CC (Configuration Channel) line of the USB Type-C connector using BMC (Biphase Mark Coding) signaling at 300 kbps. During a PD negotiation, the source advertises its power capabilities through Source Capabilities messages containing Power Data Objects (PDOs), and the sink requests a specific voltage and current combination through Request mess…

### MIPI I3C — MIPI Improved Inter-Integrated Circuit
URL: https://acutena.com/en/protocols/mipi-i3c/
Category: embedded
MIPI I3C (Improved Inter-Integrated Circuit) is a high-performance sensor interface specification developed by the MIPI Alliance as a successor to I2C and SPI for sensor and actuator communication. I3C maintains backward compatibility with I2C devices on the same bus while offering significantly higher data rates — up to 12.5 MHz in SDR (Single Data Rate) mode and up to 100 MHz in HDR (High Data Rate) modes including HDR-DDR, HDR-TSP, and HDR-TSL. Like I2C, I3C uses just two wires (SDA and SCL) but adds powerful features including dynamic address assignment, in-band interrupts (eliminating ded…

### eMMC — Embedded Multi-Media Card
URL: https://acutena.com/en/protocols/emmc/
Category: storage
eMMC (embedded MultiMediaCard) is a managed NAND flash storage interface widely used in smartphones, tablets, IoT devices, automotive infotainment systems, and embedded computing platforms. The eMMC interface consists of a CLK (clock) line, a CMD (command/response) line, and either 1, 4, or 8 DAT (data) lines operating in parallel. Modern eMMC standards (5.0 and 5.1) support data transfer rates up to 400 MB/s in HS400 mode using DDR signaling on the data lines. The protocol uses a command-response architecture where the host sends commands on the CMD line and the eMMC device responds, followed…

### CAN 2.0B — Controller Area Network 2.0B
URL: https://acutena.com/en/protocols/can-2-0b/
Category: automotive
CAN 2.0B (Controller Area Network, Part B) is the classic CAN protocol specification supporting both standard (11-bit) and extended (29-bit) message identifiers. Developed by Bosch for automotive applications, CAN 2.0B has become one of the most widely deployed communication buses in vehicles, industrial automation, medical equipment, and aerospace systems. CAN uses a differential pair (CAN H and CAN L) with bit rates up to 1 Mbps, and its multi-master architecture allows any node on the bus to initiate communication. The protocol features priority-based arbitration (lower ID values have highe…

### I2S — Inter-IC Sound
URL: https://acutena.com/en/protocols/i2s/
Category: audio
I2S (Inter-IC Sound) is a synchronous serial bus protocol designed specifically for transmitting digital audio data between integrated circuits. Developed by Philips (now NXP), I2S is the standard interface between audio codecs, DACs, ADCs, DSPs, microcontrollers, and other audio processing components. The protocol uses three signal lines: SCK (Serial Clock, also called BCLK), WS (Word Select, also called LRCLK), and SD (Serial Data). The WS signal indicates whether the left or right audio channel is being transmitted, toggling at the audio sample rate (e.g., 44.1 kHz, 48 kHz, 96 kHz, or 192 k…

### eSPI — Enhanced Serial Peripheral Interface
URL: https://acutena.com/en/protocols/espi/
Category: computing
eSPI (Enhanced Serial Peripheral Interface) is a serial bus interface developed by Intel as a replacement for the legacy LPC (Low Pin Count) bus in PC platforms. eSPI connects the Platform Controller Hub (PCH) to peripheral devices such as embedded controllers (EC), Super I/O chips, TPM modules, and BMC (Baseboard Management Controller) chips. The protocol uses a reduced pin count compared to LPC — requiring only CS , CLK, and 1, 2, or 4 I/O data lines — while providing significantly higher throughput with clock speeds up to 66 MHz and support for single, dual, and quad I/O modes. eSPI defines…

### SMBus — System Management Bus
URL: https://acutena.com/en/protocols/smbus/
Category: computing
SMBus (System Management Bus) is a two-wire communication protocol derived from I2C, specifically tailored for system management and power management functions in computing platforms. Defined by Intel and Duracell (now maintained by the SBS Forum), SMBus adds protocol-level features on top of the I2C physical layer including packet error checking (PEC using CRC-8), host notification protocol, alert response, and standardized command sets. SMBus operates at up to 100 kHz (SMBus 1.x) or 400 kHz (SMBus 2.0) and optionally up to 1 MHz (SMBus 3.0) using the SDA and SCL lines. The protocol is critic…

### PMBus — Power Management Bus
URL: https://acutena.com/en/protocols/pmbus/
Category: power
PMBus (Power Management Bus) is an open-standard power management protocol built on top of SMBus, designed for digital communication with and control of power conversion devices such as voltage regulators (VRMs), DC-DC converters, power supplies, and power sequencing controllers. The PMBus specification defines a comprehensive set of standardized commands for setting output voltage, configuring current limits, reading telemetry data (voltage, current, temperature, power), managing fault responses, and controlling power supply sequencing. PMBus uses the same two-wire SDA/SCL interface as SMBus…

### SD UHS — SD/SDIO UHS-I/UHS-II
URL: https://acutena.com/en/protocols/sd-uhs/
Category: storage
SD UHS (Ultra High Speed) encompasses the UHS-I and UHS-II interface specifications for SD memory cards, offering significantly faster data transfer rates than legacy SD modes. UHS-I operates on the standard SD interface with a single row of pins, supporting SDR50 (50 MB/s), SDR104 (104 MB/s), and DDR50 (50 MB/s DDR) transfer modes at 1.8V signaling. UHS-II adds a second row of pins to the SD connector, providing two additional differential lanes (D0 and D1) for full-duplex communication at up to 312 MB/s per lane. The SD protocol uses a command-response architecture with CMD and DAT lines, wh…

### QSPI — Quad SPI
URL: https://acutena.com/en/protocols/qspi/
Category: storage
QSPI (Quad SPI) is an enhanced version of the SPI protocol that uses four data lines instead of one, quadrupling the data throughput while maintaining the same clock frequency. QSPI is the predominant interface for NOR flash memory devices used to store firmware, boot code, configuration data, and application code in embedded systems, networking equipment, automotive ECUs, and consumer electronics. In QSPI mode, the traditional MOSI and MISO lines are repurposed as IO0 and IO1, with two additional lines IO2 and IO3 added for four-bit parallel data transfer. The protocol supports multiple opera…

### SVID — Intel Serial Voltage Identification
URL: https://acutena.com/en/protocols/svid/
Category: power
SVID (Serial Voltage Identification) is a proprietary serial interface developed by Intel for communication between Intel processors and voltage regulator modules (VRMs) on motherboards and computing platforms. SVID enables the processor to dynamically request specific voltage levels from the VRM, supporting Intel's power management features including SpeedStep, Turbo Boost, and various low-power states. The protocol uses three signal lines — SCLK, SDATA, and ALERT — operating at up to 26.25 MHz with a command-response architecture. The processor sends commands to set voltage (SetVID), request…

### MIPI RFFE — MIPI RF Front-End
URL: https://acutena.com/en/protocols/mipi-rffe/
Category: mobile
MIPI RFFE (RF Front-End Control Interface) is a compact, high-speed serial interface developed by the MIPI Alliance for controlling RF front-end components in mobile devices. RFFE connects the baseband processor or RF transceiver to power amplifiers, antenna tuners, antenna switch modules, low-noise amplifiers, and other RF components using just two signal lines: SCLK and SDATA. The protocol operates at clock speeds up to 26 MHz and supports single-bit and multi-bit data transfers with a command-response architecture. RFFE defines several transaction types including register write, register re…

### DP AUX — DisplayPort Auxiliary Channel
URL: https://acutena.com/en/protocols/dp-aux/
Category: display
The DisplayPort AUX (Auxiliary) channel is a half-duplex bidirectional serial interface used for sideband communication in DisplayPort and eDP (embedded DisplayPort) connections. Operating at 1 MHz Manchester-encoded signaling on a single differential pair (AUX CH P and AUX CH N), the AUX channel handles critical functions including EDID/DisplayID reading, DPCD (DisplayPort Configuration Data) register access, link training negotiation, content protection (HDCP) authentication, and MST (Multi-Stream Transport) sideband messaging. The source device (GPU or display controller) initiates transact…

### Modbus — Modbus RTU/TCP
URL: https://acutena.com/en/protocols/modbus/
Category: industrial
Modbus is a serial communication protocol originally published by Modicon in 1979, now one of the most widely used protocols in industrial automation, building management, energy systems, and SCADA applications. Modbus defines a master-slave (client-server) architecture where one master device communicates with up to 247 slave devices. Two primary serial variants exist: Modbus RTU (binary encoding with CRC-16 error checking) and Modbus ASCII (ASCII hex encoding with LRC error checking). Modbus RTU is the more common variant, operating over RS-232, RS-422, or RS-485 physical layers at baud rate…

### JTAG — Joint Test Action Group (IEEE 1149.1)
URL: https://acutena.com/en/protocols/jtag/
Category: embedded
JTAG (Joint Test Action Group) is a debug and test interface standardized as IEEE 1149.1, originally designed for boundary scan testing of circuit boards but now widely used for IC programming, debugging, and real-time trace in embedded systems. The JTAG interface uses a TAP (Test Access Port) with four required signals: TCK (Test Clock), TMS (Test Mode Select), TDI (Test Data In), and TDO (Test Data Out), plus an optional TRST (Test Reset). The TAP controller is a 16-state finite state machine driven by TCK and TMS, through which instructions and data are shifted in and out via TDI and TDO. J…

### MIPI SPMI — MIPI System Power Management Interface
URL: https://acutena.com/en/protocols/mipi-spmi/
Category: power
MIPI SPMI (System Power Management Interface) is a two-wire serial interface developed by the MIPI Alliance for communication between application processors and power management ICs (PMICs) in mobile devices. SPMI uses SCLK and SDATA lines operating at up to 26 MHz, providing a high-speed, low-pin-count connection for controlling voltage regulators, battery chargers, GPIO expanders, ADCs, and other power management functions integrated into the PMIC. The protocol supports up to 16 master IDs and 16 slave IDs on a single bus, with transaction types including register write, register read, exten…

### PDM — Pulse Density Modulation
URL: https://acutena.com/en/protocols/pdm/
Category: audio
PDM (Pulse Density Modulation) is a single-bit digital audio encoding used primarily as the output format for MEMS digital microphones. A PDM stream consists of a clock signal (CLK) driven by the host and a data signal (DATA) driven by the microphone, where the density of logic-high pulses represents the instantaneous amplitude of the audio signal. PDM microphones are found in smartphones, laptops, smart speakers, hearing aids, and IoT devices due to their small size and simple two-wire interface. Engineers debugging PDM interfaces need to verify clock frequency accuracy, confirm left/right ch…

### MIPI SoundWire — MIPI SoundWire Audio Interface
URL: https://acutena.com/en/protocols/mipi-soundwire/
Category: audio
MIPI SoundWire is a next-generation audio interface standard designed to replace legacy audio buses like I2S, SLIMbus, and proprietary codec interfaces in mobile and computing platforms. It uses a two-wire interface (clock and data) to carry multiple audio streams, control commands, and bulk data transfers over a single bus. SoundWire supports multi-device topologies with up to 11 peripheral devices, dynamic channel allocation, and clock scaling for power efficiency. Engineers working with modern audio codecs, amplifiers, and microphone arrays on SoundWire need protocol-level visibility to deb…

### PCM — Pulse Code Modulation
URL: https://acutena.com/en/protocols/pcm/
Category: audio
PCM (Pulse Code Modulation) in the context of digital audio interfaces refers to the synchronous serial bus commonly used for telephony, Bluetooth audio, and voice processing applications. A PCM interface uses four signals: CLK (bit clock), SYNC (frame sync), DIN (data in), and DOUT (data out). Unlike I2S which is designed for stereo hi-fi audio, the PCM interface is optimized for voice-bandwidth audio at 8 kHz or 16 kHz sample rates with 8-bit or 16-bit resolution. PCM interfaces are widely found connecting Bluetooth modules, cellular modems, and voice codecs to baseband processors. Engineers…

### TDM — Time Division Multiplexing
URL: https://acutena.com/en/protocols/tdm/
Category: audio
TDM (Time Division Multiplexing) is a multi-channel audio transport scheme that carries multiple audio channels on a single serial data line by assigning each channel to a specific time slot within a repeating frame. TDM is used in professional audio systems, telecommunications equipment, audio DSP arrays, and multi-codec architectures where more than two audio channels must share a bus. The interface typically uses CLK, SYNC (frame sync), and one or more DATA lines, with frame sizes ranging from 2 to 32 or more time slots. Engineers debugging TDM buses need to verify time-slot assignments, fr…

### Ethernet MCTP — Management Component Transport Protocol over Ethernet
URL: https://acutena.com/en/protocols/ethernet-mctp/
Category: computing
MCTP over Ethernet (Management Component Transport Protocol) is a DMTF standard that enables platform management communication between a baseboard management controller (BMC) and managed components using Ethernet as the physical transport. It encapsulates MCTP messages in Ethernet frames using a dedicated EtherType, enabling management traffic to share the same network infrastructure as data traffic. This protocol is used in servers, data center equipment, and platform management architectures where components like NICs, GPUs, storage controllers, and FPGAs need to communicate with the BMC. En…

### LTPI — Low Throughput Peripheral Interface
URL: https://acutena.com/en/protocols/ltpi/
Category: computing
LTPI (Low Throughput Peripheral Interface) is an Intel-defined serial bus used for communication between a host processor or BMC and platform peripherals in server and computing platforms. LTPI provides a lightweight, low-pin-count alternative to eSPI for connecting peripherals that do not require high bandwidth, such as GPIO expanders, fan controllers, and basic I/O devices. The interface uses a synchronous clock and data pair, operating at speeds up to 24 MHz. Engineers working on Intel server platform bring-up and debug need LTPI decode capability to verify peripheral enumeration, command/r…

### MCTP Control — MCTP Control Messages
URL: https://acutena.com/en/protocols/mctp-control/
Category: computing
MCTP Control Messages form the base management layer of the DMTF Management Component Transport Protocol. These messages handle endpoint discovery, endpoint ID (EID) assignment, routing table management, and message integrity verification across all MCTP transport bindings (SMBus, Ethernet, PCIe VDM). The MCTP control protocol is essential for establishing the management communication fabric in servers and data center platforms, enabling the BMC to discover and communicate with all managed components. Engineers debugging platform management issues need to decode MCTP control messages to verify…

### PLDM — Platform Level Data Model over MCTP
URL: https://acutena.com/en/protocols/pldm-mctp/
Category: computing
PLDM (Platform Level Data Model) is a DMTF specification that defines structured data formats and message commands for platform management functions transported over MCTP. PLDM covers sensor monitoring and events, firmware update, BIOS configuration, and Redfish Device Enablement (RDE). It provides the application-layer semantics that BMCs and managed devices use to exchange telemetry, perform firmware updates, and manage platform configuration. Engineers debugging server and data center platform management need PLDM decode to verify sensor readings, firmware update sequences, event handling,…

### M-PESTI — Management Peripheral Encapsulation of Sideband Transport Interface
URL: https://acutena.com/en/protocols/m-pesti/
Category: computing
M-PESTI (Management Peripheral Encapsulation of Sideband Transport Interface) is an Intel-defined protocol for encapsulating management peripheral traffic over a sideband transport link in server and computing platforms. M-PESTI enables platform management controllers to communicate with remote peripherals over a serial interface, consolidating multiple management bus functions onto a single link. The protocol is used in modern Intel server architectures to reduce pin count and simplify management bus routing. Engineers working on Intel platform bring-up need M-PESTI decode capability to debug…

### NCSI — Network Controller Sideband Interface over MCTP/RMII
URL: https://acutena.com/en/protocols/ncsi-mctp/
Category: computing
NC-SI (Network Controller Sideband Interface) is a DMTF standard that enables a baseboard management controller (BMC) to configure and manage network controllers (NICs) through a dedicated sideband channel. NC-SI can be transported over MCTP or directly over an RMII interface. The protocol handles NIC configuration commands such as enabling management traffic passthrough, setting MAC address filters, and querying link status — all without using the main network data path. Engineers debugging server network connectivity, BMC-to-NIC communication failures, and management network configuration ne…

### SPDM — Security Protocol and Data Model over MCTP
URL: https://acutena.com/en/protocols/spdm-mctp/
Category: computing
SPDM (Security Protocol and Data Model) is a DMTF specification for device authentication, measurement, and attestation transported over MCTP. SPDM enables a verifier (typically a BMC or host) to authenticate managed components such as NICs, GPUs, storage controllers, and FPGAs by exchanging certificates, performing challenge-response authentication, and retrieving device measurements. SPDM is becoming a critical requirement in data center security architectures for establishing hardware root of trust. Engineers debugging platform security need SPDM decode to verify the authentication handshak…

### USB4/TBT3 SB — USB4 / Thunderbolt 3 Sideband Channel
URL: https://acutena.com/en/protocols/usb4-tbt3-sb/
Category: computing
The USB4 / Thunderbolt 3 Sideband Channel is a low-speed serial interface used by the USB4 connection manager to communicate with routers and retimers for link initialization, tunneling configuration, and power management. The sideband channel operates on dedicated sideband pins separate from the high-speed data lanes. It carries configuration space reads/writes, notification messages, and control commands that set up DisplayPort tunneling, PCIe tunneling, and USB 3.x tunneling over the USB4/Thunderbolt link. Engineers debugging USB4 docking stations, Thunderbolt peripherals, and host controll…

### MIPI D-PHY — MIPI D-PHY Physical Layer
URL: https://acutena.com/en/protocols/mipi-dphy/
Category: display
MIPI D-PHY is the physical layer specification used by MIPI CSI-2 (camera) and MIPI DSI (display) interfaces. It defines a source-synchronous, differential serial interface with two operating modes: a high-speed (HS) mode for burst data transfer at up to 2.5 Gbps per lane, and a low-power (LP) mode for control signaling at up to 10 Mbps. D-PHY uses differential clock and data lane pairs, with each data lane capable of independent LP signaling on its individual positive and negative lines. Engineers debugging camera sensor bring-up, display initialization, and mobile platform video paths need D…

### MIPI DSI LP — MIPI DSI Low-Power Mode
URL: https://acutena.com/en/protocols/mipi-dsi-lp/
Category: display
MIPI DSI Low-Power (LP) mode is the command channel of the MIPI Display Serial Interface, used for display panel initialization, configuration, and status queries. While DSI high-speed mode carries pixel data at multi-Gbps rates, LP mode operates at up to 10 Mbps on the D-PHY data lane LP signals. LP mode carries DCS (Display Command Set) commands, manufacturer-specific commands, and generic read/write packets that configure display timing, gamma, power mode, and other panel parameters. Engineers debugging display bring-up issues need to decode DSI LP mode to verify initialization command sequ…

### MII — Media Independent Interface
URL: https://acutena.com/en/protocols/mii/
Category: computing
MII (Media Independent Interface) is the standard parallel interface between an Ethernet MAC controller and a PHY transceiver for 10/100 Mbps Ethernet. Defined in IEEE 802.3u, MII uses separate 4-bit-wide transmit and receive data paths, each with its own clock, plus control signals for carrier sense, collision detection, and data valid indication. MII operates at 2.5 MHz for 10 Mbps Ethernet and 25 MHz for 100 Mbps. Engineers debugging Ethernet connectivity at the hardware level use MII analysis to verify data framing, clock timing, and MAC-PHY communication during link establishment and pack…

### RMII — Reduced Media Independent Interface
URL: https://acutena.com/en/protocols/rmii/
Category: computing
RMII (Reduced Media Independent Interface) is a simplified version of MII that reduces the pin count for 10/100 Mbps Ethernet MAC-to-PHY connections. RMII uses 2-bit-wide transmit and receive data paths (instead of 4-bit), sharing a single 50 MHz reference clock (instead of separate TX and RX clocks). This reduced pin count makes RMII popular in space-constrained designs and microcontrollers with limited pin availability. The trade-off is a higher clock frequency and tighter timing requirements. Engineers debugging embedded Ethernet implementations frequently encounter RMII interface issues re…

### RGMII — Reduced Gigabit Media Independent Interface
URL: https://acutena.com/en/protocols/rgmii/
Category: computing
RGMII (Reduced Gigabit Media Independent Interface) is the most widely used MAC-to-PHY interface for Gigabit Ethernet in embedded systems. RGMII achieves 1 Gbps throughput using only 12 signals by employing DDR (Double Data Rate) signaling — data is sampled on both the rising and falling edges of the 125 MHz clock. This makes RGMII timing-critical, as clock-to-data alignment must be maintained within tight margins. RGMII supports 10/100/1000 Mbps operation, with the clock frequency scaling accordingly. Engineers debugging Gigabit Ethernet frequently encounter RGMII timing issues including inte…

### GMII — Gigabit Media Independent Interface
URL: https://acutena.com/en/protocols/gmii/
Category: computing
GMII (Gigabit Media Independent Interface) is the original 8-bit-wide parallel interface for Gigabit Ethernet MAC-to-PHY connections, defined in IEEE 802.3z. GMII uses separate 8-bit transmit and receive data buses clocked at 125 MHz, providing 1 Gbps throughput without requiring DDR signaling. While RGMII has largely replaced GMII in new designs due to its lower pin count, GMII is still found in FPGA-based Ethernet implementations, network equipment, and legacy designs where the wider bus and simpler SDR timing are advantageous. Engineers working with GMII need to verify data bus timing, cloc…

### SGMII — Serial Gigabit Media Independent Interface
URL: https://acutena.com/en/protocols/sgmii/
Category: computing
SGMII (Serial Gigabit Media Independent Interface) is a serial alternative to GMII and RGMII for Gigabit Ethernet MAC-to-PHY connections. Originally defined by Cisco, SGMII uses a single differential pair in each direction (TX+/-, RX+/-) running at 1.25 Gbps with 8b/10b encoding. SGMII drastically reduces pin count to just 4 signal pins (plus optional reference clock), making it popular in switch ICs, SoCs, and multi-port Ethernet designs where routing many parallel data lines is impractical. Engineers debugging SGMII links need to verify the serial data encoding, auto-negotiation, and link st…

### SVI3 — AMD Serial VID Interface 3
URL: https://acutena.com/en/protocols/svi3/
Category: power
SVI3 (Serial VID Interface 3) is AMD's proprietary serial bus protocol for communication between AMD processors and voltage regulator modules (VRMs). SVI3 uses three signals — SVC (clock), SVD (data), and SVT (telemetry) — to manage dynamic voltage and frequency scaling. The protocol enables the processor to command voltage changes, read VRM telemetry (current, temperature), and manage power states. SVI3 operates at clock speeds up to 50 MHz with a voltage range of 1.08V to 1.98V, and includes features for fast transient response and power state management that are critical for AMD Ryzen and E…

### Power Sequence — Power Sequence Validation (16–128 channels)
URL: https://acutena.com/en/protocols/power-sequence/
Category: power
Power Sequence Validation is a multi-channel digital capture capability designed to verify the timing and order of power rail enable signals and power-good (PG) outputs during system power-up and power-down. Modern electronic systems have dozens of power rails that must ramp in a specific order with precise timing relationships — incorrect sequencing can cause latch-up, component damage, or silent initialization failures. The MSO2216B is Acute's recommended instrument for power sequence validation , providing 16 channels per unit with multi-unit cascading: cascade 2 MSO2216B for 32 channels, s…

### BiSS-C — BiSS-C Serial Sensor Interface
URL: https://acutena.com/en/protocols/biss-c/
Category: industrial
BiSS-C (Bidirectional Synchronous Serial interface, continuous mode) is an open-standard serial protocol for connecting position encoders, angle sensors, and other precision measurement devices to controllers in industrial motion control systems. BiSS-C uses two signals: MA (Master clock/Acknowledge) driven by the controller and SLO (Slave output) driven by the sensor. The master generates a clock on MA, and the sensor responds with position data, status bits, and CRC on SLO. BiSS-C supports high-resolution absolute position data at clock rates up to 10 MHz and includes error detection through…

### HDLC — High-Level Data Link Control
URL: https://acutena.com/en/protocols/hdlc/
Category: industrial
HDLC (High-Level Data Link Control) is a bit-oriented data link layer protocol defined in ISO 13239, widely used in telecommunications, industrial control, and legacy serial communication systems. HDLC provides a framing mechanism using flag sequences (0x7E), bit-stuffing for transparency, address and control fields, and FCS (Frame Check Sequence) error detection. HDLC is the foundation for many derived protocols including SDLC, LAPB (X.25), LAPD (ISDN), and PPP framing. Engineers debugging telecom interfaces, legacy industrial networks, and point-to-point serial links encounter HDLC framing i…

### ProfiBus — Process Field Bus
URL: https://acutena.com/en/protocols/profibus/
Category: industrial
ProfiBus (Process Field Bus) is a widely deployed industrial fieldbus standard defined in IEC 61158, used for communication between PLCs, I/O modules, drives, sensors, and actuators in factory automation and process control systems. ProfiBus DP (Decentralized Peripherals) is the most common variant, operating over RS-485 at speeds up to 12 Mbps for fast I/O communication. ProfiBus PA (Process Automation) uses MBP (Manchester Bus Powered) signaling for intrinsically safe process instrumentation. The protocol uses a token-passing mechanism among master devices and a master-slave model for I/O co…

### PWM — Pulse Width Modulation
URL: https://acutena.com/en/protocols/pwm/
Category: industrial
PWM (Pulse Width Modulation) is a digital signaling technique where information is encoded in the duty cycle (ratio of high time to total period) of a rectangular waveform. PWM is universally used in embedded systems for motor speed control, LED brightness dimming, servo positioning, power converter regulation, and DAC emulation. While PWM is not a communication protocol in the traditional sense, analyzing PWM signals is essential for verifying correct duty cycle, frequency, dead time in H-bridge configurations, and timing accuracy. Engineers debugging motor controllers, LED drivers, switching…

### NAND Flash — Parallel NAND Flash Interface
URL: https://acutena.com/en/protocols/nand-flash/
Category: storage
Parallel NAND Flash is the raw interface used to communicate with NAND flash memory devices, providing direct access to the flash command set for read, program, erase, and status operations. The interface uses an 8-bit bidirectional data bus (IO[7:0]) along with control signals including CLE (Command Latch Enable), ALE (Address Latch Enable), WE (Write Enable), RE (Read Enable), and CE (Chip Enable). Modern NAND flash devices conforming to ONFI 4.0 can operate at up to 200 MHz with DDR signaling. Engineers debugging embedded storage systems, SSD controllers, and NAND-based designs need paralle…

### Serial NOR Flash — Serial NOR Flash (SPI Flash)
URL: https://acutena.com/en/protocols/serial-nor-flash/
Category: storage
Serial NOR Flash (commonly called SPI Flash) is the dominant non-volatile storage technology for firmware, boot code, and configuration data in embedded systems. These devices communicate over a standard SPI interface (CLK, CS , MOSI/IO0, MISO/IO1), with many modern devices also supporting Dual SPI and Quad SPI modes for higher throughput. Serial NOR flash is used as the boot ROM in virtually every computing platform — from microcontrollers to servers — storing BIOS/UEFI firmware, FPGA bitstreams, and application code. Engineers debugging boot failures, firmware corruption, and flash programmi…

### SPI NAND — SPI NAND Flash
URL: https://acutena.com/en/protocols/spi-nand/
Category: storage
SPI NAND Flash combines NAND flash storage density with a simple SPI serial interface, providing a cost-effective storage solution for embedded systems that need more capacity than NOR flash but do not require a parallel NAND controller. SPI NAND devices use the same CLK, CS , and IO0-3 signals as SPI NOR flash but implement the NAND command set with page-based read/program operations and block-based erase. The SPI interface operates at clock speeds up to 133 MHz in Quad I/O mode. Engineers debugging SPI NAND storage encounter challenges with page read sequences (command, address, dummy, data)…

### 10BASE-T1S — 10BASE-T1S Automotive Ethernet
URL: https://acutena.com/en/protocols/10base-t1s/
Category: automotive
10BASE-T1S is an IEEE 802.3cg Ethernet standard designed for multi-drop, single twisted-pair automotive and industrial networks. Unlike traditional point-to-point Ethernet, 10BASE-T1S supports a multi-drop bus topology with up to 8 or more nodes sharing a single cable segment, using PLCA (Physical Layer Collision Avoidance) to manage medium access. Operating at 10 Mbps over a single unshielded twisted pair, 10BASE-T1S is positioned as a modern replacement for CAN and LIN in vehicle zone architectures, connecting sensors, actuators, and low-bandwidth ECUs. Engineers developing automotive Ethern…

### OA3p — OPEN Alliance 3rd Party
URL: https://acutena.com/en/protocols/oa3p/
Category: automotive
OA3p (OPEN Alliance 3rd Party) refers to the conformance and interoperability testing framework defined by the OPEN Alliance SIG for automotive Ethernet components. The OPEN Alliance ecosystem encompasses physical layer compliance testing, interoperability verification, and protocol conformance for automotive Ethernet implementations including 10BASE-T1S, 100BASE-T1, and 1000BASE-T1. Engineers working with OPEN Alliance-certified components need protocol analysis tools to verify compliance with OPEN Alliance specifications, debug interoperability issues between components from different vendor…

### OPEN Alliance TC6 — OPEN Alliance TC6 10BASE-T1S MAC-PHY
URL: https://acutena.com/en/protocols/open-alliance-tc6/
Category: automotive
OPEN Alliance TC6 defines the SPI-based interface between a host controller and a 10BASE-T1S MAC-PHY device. Instead of implementing the Ethernet MAC in the host, TC6 MAC-PHY devices integrate both MAC and PHY functions, exposing a simple SPI interface for the host to send and receive Ethernet frames. The TC6 protocol defines the SPI frame format, header structure, data chunk transfer, and control commands for configuration, status polling, and frame transfer. Engineers developing automotive Ethernet nodes using TC6 MAC-PHY chips need to debug the SPI-level communication to verify frame transf…

### USB 1.1 — Universal Serial Bus 1.1
URL: https://acutena.com/en/protocols/usb-1-1/
Category: embedded
USB 1.1 (Universal Serial Bus 1.1) is the original widely-deployed USB specification, supporting Low Speed (1.5 Mbps) and Full Speed (12 Mbps) data transfer over a differential D+/D- signal pair. USB 1.1 devices are still manufactured and widely used — keyboards, mice, microcontrollers with built-in USB, HID devices, CDC serial adapters, and many industrial/medical devices use USB 1.1 Full Speed. The protocol includes device enumeration, descriptor exchange, control/bulk/interrupt/isochronous transfer types, and hub-managed bus topology. Engineers debugging USB 1.1 devices need to analyze enum…

### SWD — Serial Wire Debug
URL: https://acutena.com/en/protocols/swd/
Category: embedded
SWD (Serial Wire Debug) is a two-pin debug interface defined by ARM as part of the CoreSight debug architecture. SWD provides the same debug functionality as JTAG — register access, memory read/write, breakpoints, and trace — using only two pins: SWDIO (bidirectional data) and SWCLK (clock). SWD is the standard debug interface for ARM Cortex-M, Cortex-A, and Cortex-R processors, making it ubiquitous in microcontroller and embedded processor designs. Engineers analyzing SWD traffic can verify that debug probes are communicating correctly with the target, diagnose firmware download failures, and…

## Learn Articles

### How to Choose the Right Logic Analyzer for Your Project
URL: https://acutena.com/en/learn/choosing-logic-analyzer-guide/
Category: how-to · Published: 2026-04-01
A practical decision guide for selecting the right Acute logic analyzer or mixed-signal oscilloscope based on your channel count, sample rate, protocol decode, and portability requirements.
Why the Choice Matters Selecting the wrong test instrument costs more than money. An analyzer with too few channels forces you to swap probes repeatedly, missing correlated events across signals. Insufficient sample rate produces incorrect decodes and phantom glitches. Too little memory depth means you capture only a fraction of the behavior you need to see. On the other hand, over-specifying the instrument wastes budget that could go toward other equipment. This guide walks through the key decision factors and maps them to the Acute instrument lineup, helping you select the right tool without over-spending or under-specifying. Key Decision Factors Channel Count Channel count is the most fundamental specification. Count every signal you need to observe simultaneously: - Protocol buses : I2C needs 2 channels (SDA, SCL). SPI needs 3-4 (CLK, MOSI, MISO, CS). UART needs 1-2 (TX, RX). eSPI needs 4-8 (CLK, CS, IO[0-3], ALERT, RESET). MIPI I3C needs 2 (SDA, SCL). - Address/data buses : A 16-bit parallel data bus plus control signals can consume 20+ channels. - Debug signals : Chip selects, interrupt lines, enable pins, GPIO status outputs. - Margin : Add 20-30% to your count for signals you did not initially plan to capture but will inevitably need during debug. Acute offers instruments from 16 channels (TravelLogic compact models) through 36, 72, and 144 channels (LA4000 series), with cascading options that extend to 288+ channels. Sample Rate The required sample rate depends on the fastest signal you need to capture: - Rule of thumb : 5x the signal frequency for basic state obse…

### PX2816B Protocol Exerciser: Stimulus and Response Testing for Embedded Interfaces
URL: https://acutena.com/en/learn/px2816b-protocol-exerciser-guide/
Category: product-spotlight · Published: 2026-03-20
How the PX2816B Protocol Exerciser enables engineers to generate protocol stimulus, validate device responses, and automate compliance testing for I2C, SPI, UART, and MIPI I3C interfaces.
Protocol Exerciser vs Protocol Analyzer A protocol analyzer is a passive instrument. It monitors bus traffic, captures data, and decodes frames -- but it never drives any signals. An analyzer tells you what happened on the bus. A protocol exerciser is an active instrument. It generates protocol transactions, drives signals onto the bus, and reads back responses from target devices. An exerciser lets you control what happens on the bus. The distinction matters because many embedded debugging scenarios require both capabilities. If a sensor is not responding to I2C reads, an analyzer can confirm the silence, but it cannot tell you whether the problem is the sensor or the master. An exerciser replaces the master, sends known-good transactions, and reveals whether the sensor responds correctly when addressed properly. The Acute PX2816B Protocol Exerciser fills this active-stimulus role. It supports I2C, SPI, UART, and MIPI I3C protocols, generating fully configurable transactions from a PC-based interface. When paired with an Acute logic analyzer or protocol analyzer, it creates a complete stimulus-and-capture workflow: the exerciser drives the bus while the analyzer records every signal transition for detailed post-capture analysis. Key Use Cases Device Validation When bringing up a new IC or module, you need to verify that it responds correctly to protocol transactions before integrating it with production firmware. The PX2816B lets you send individual read and write transactions to specific addresses and registers, confirming device identity registers, configuration register…

### Power Sequence Validation with Acute Logic Analyzers
URL: https://acutena.com/en/learn/power-sequence-validation/
Category: application-note · Published: 2026-03-15
Learn how to validate multi-rail power-up and power-down sequences on FPGA and SoC designs using Acute logic analyzers with 16-128 channel simultaneous capture.
Why Power Sequencing Matters Modern FPGAs and SoCs require multiple voltage rails brought up in a precise order with specific timing constraints. A Xilinx UltraScale+ device, for instance, may require VCCINT (0.85V), VCCAUX (1.8V), VCCBRAM (0.85V), and VCCO banks (1.2V-3.3V) to energize in a defined sequence with minimum and maximum ramp-rate constraints between each rail. Violating these requirements can cause latch-up, excessive inrush current, or permanent silicon damage. Power-down sequencing is equally critical. If a high-voltage I/O rail remains energized after the core supply drops, ESD protection structures in the die can forward-bias and create destructive current paths. Datasheet power-down requirements are often stricter than power-up requirements, yet they receive far less validation attention during board bring-up. The Multi-Rail Validation Challenge Validating power sequences on a production board is harder than it appears. A typical FPGA carrier board has 8-15 distinct voltage rails, each generated by a separate regulator or PMBus-controlled power module. You need to observe the relative timing of all rails simultaneously -- not just two at a time on an oscilloscope. Additionally, you need to verify the enable-signal sequencing coming from the board management controller (BMC) or CPLD that orchestrates power-up. Traditional oscilloscopes are limited to 4 analog channels. You could multiplex measurements across several power cycles, but rail-to-rail timing varies from cycle to cycle due to regulator soft-start variation, input voltage droop, and temperature. C…

### How to Cascade Acute Oscilloscopes for More Synchronized Analog Channels
URL: https://acutena.com/en/learn/device-cascading-guide/
Category: how-to · Published: 2026-03-01
Step-by-step guide to cascading multiple Acute oscilloscopes for synchronized multi-instrument analog capture. Covers TravelScope and the DSO functionality of MSO3000 series.
Important: Cascading Applies to Analog (DSO) Channels Only A common misconception is that Acute logic analyzers can be cascaded for higher digital channel counts. They cannot. Only the oscilloscope (DSO) functionality of Acute instruments supports multi-unit cascading. This means: - TravelScope (pure PC-based oscilloscopes) — supported - MSO3000 series — only the analog scope channels of MSO units can be cascaded; the digital logic analyzer channels do not cascade - TravelLogic, LA4000, and other pure logic analyzers — do not support cascading If you need more digital channels than a single Acute logic analyzer provides, the correct path is to choose a higher-channel-count single unit (e.g., LA4136E/B at 136 channels) rather than attempting to cascade smaller units. When You Need Cascading A single Acute oscilloscope provides up to 4 analog channels. For most bench debugging this is plenty, but several scenarios demand more synchronized analog channels than one instrument offers: - Multi-rail power validation : A modern SoC can have 8+ independent power rails, each with its own ramp, sequencing, and ripple characteristics. Capturing all rails simultaneously during a boot sequence requires more than 4 analog channels with sample-accurate alignment. - Multi-clock domain analysis : Verifying skew between several clock signals (e.g., DDR DQS strobes, reference clocks, recovered clocks) requires simultaneous analog capture on every clock to measure phase relationships. - Differential signal pair characterization : Analyzing multiple high-speed differential pairs (P/N) for skew a…

### Getting Started with Acute Test Instruments
URL: https://acutena.com/en/learn/getting-started-acute-instruments/
Category: how-to · Published: 2026-03-01
First-time setup guide for Acute instruments — software installation, USB connection, first capture, and basic protocol decode configuration for I2C, SPI, and UART.
What Is in the Box Acute instruments ship with a consistent set of accessories, though specifics vary by model: - The instrument (TravelLogic, TravelBus, MSO3000, LA4000, or other model) - USB cable (USB 3.0 Type-A to Type-B or Type-C, depending on the model) - Logic analyzer probe cables with grabber clips (for logic analyzer and MSO digital channels) - Ground leads (short spring-ground tips and longer fly-wire leads) - Calibration certificate - Quick start card with download URL for the software For MSO and TravelBus models, the box also includes oscilloscope probes for the analog channels. For the LA4000 and LA3000 bench models, a power supply is included (portable models like TravelLogic and TravelBus are USB-powered and do not require an external supply). Check that all listed accessories are present before proceeding. If anything is missing, contact Acute North America support. Software Download and Installation System Requirements - Operating system : Windows 10 (64-bit) or Windows 11 (64-bit). A native Linux app (beta) is also available for several product families: TravelBus, TravelLogic, MSO3000, TravelScope, and BusFinder / LA4000. - USB : USB 3.0 port required (USB 2.0 will work for connection but limits data transfer speed) - Disk space : Approximately 500 MB for the full installation - RAM : 8 GB minimum, 16 GB recommended for large captures Installation Steps 1. Visit the Acute North America downloads page and download the latest version of the Acute software package. 2. Run the installer executable. If Windows SmartScreen presents a warning, click More info…

### Complete Guide to I2C Bus Debugging
URL: https://acutena.com/en/learn/i2c-debugging-guide/
Category: protocol-guide · Published: 2026-02-15
Practical guide to I2C protocol debugging using Acute instruments — from basic decode setup to advanced trigger configurations for catching elusive bus errors.
I2C Fundamentals Recap I2C (Inter-Integrated Circuit) is a two-wire serial bus using a clock line (SCL) and a data line (SDA). Both lines are open-drain, pulled high by external resistors, and driven low by devices on the bus. Communication follows a master-slave model: the master generates the clock and initiates transactions. Each transaction begins with a START condition (SDA falling while SCL is high) and ends with a STOP condition (SDA rising while SCL is high). A standard I2C frame consists of a 7-bit address (or 10-bit in extended mode), a read/write bit, and one or more data bytes. After each byte, the receiver must pull SDA low during the 9th clock cycle to send an ACK. If SDA remains high, it is a NACK, indicating an error or end of transfer. Standard mode runs at 100 kHz, fast mode at 400 kHz, fast mode plus at 1 MHz, and high-speed mode at 3.4 MHz. SMBus is a subset of I2C with stricter timing and voltage specifications, commonly used for power management and system monitoring. Setting Up I2C Decode on Acute Instruments Physical Connections Connect two logic analyzer channels (or two analog channels on an MSO) to SDA and SCL. Always connect the analyzer's ground lead to the target board's ground at a point close to the I2C bus. For logic analyzer connections: - Set the threshold voltage to match the bus voltage. For 3.3V I2C, a threshold of 1.5V works well. For 1.8V I2C, use 0.8V. - If using an MSO2000 or MSO3000 in analog mode, you can observe the actual voltage waveforms and identify signal integrity issues that a logic analyzer alone would miss. Pull-Up Resis…

### MIPI I3C Protocol Analysis: Capturing and Debugging Next-Gen Sensor Buses
URL: https://acutena.com/en/learn/mipi-i3c-analysis-guide/
Category: protocol-guide · Published: 2026-02-10
Complete guide to MIPI I3C protocol analysis — from basic bus capture to advanced HDR mode decode, in-band interrupts, and I2C backward compatibility validation.
I3C vs I2C: What Changed and Why It Matters MIPI I3C was designed as a direct successor to I2C, addressing the limitations that became apparent as sensor counts and data rates increased in mobile, IoT, and automotive systems. The key differences are substantial. Speed : I2C tops out at 3.4 MHz in high-speed mode (and most implementations use 400 kHz or 1 MHz). I3C SDR (Single Data Rate) mode runs at up to 12.5 MHz, and HDR (High Data Rate) modes push effective throughput to 25 Mbps or higher. Interrupt mechanism : I2C has no standard interrupt mechanism -- devices use separate GPIO lines to signal the host. I3C introduces in-band interrupts (IBI), allowing any target device to request attention directly on the SDA line without additional pins. Dynamic addressing : I2C devices have fixed or pin-configurable addresses, which can cause conflicts when multiple identical devices are on the same bus. I3C assigns addresses dynamically during bus initialization, eliminating address conflicts. Pin compatibility : I3C uses the same two-wire SDA/SCL interface as I2C and supports legacy I2C devices on the same bus. This backward compatibility is a major factor in adoption -- teams can migrate to I3C incrementally. Power and pins : By eliminating dedicated interrupt lines and using dynamic addressing (removing address-select pins), I3C reduces total pin count per device, which matters in space-constrained designs like smartphones and wearables. Why I3C Analysis Requires Specialized Tools I3C's higher data rates, dual-mode operation (SDR and HDR), and in-band interrupts make it significa…

### CAN FD Protocol Analysis for Automotive Electronics
URL: https://acutena.com/en/learn/can-fd-analysis/
Category: protocol-guide · Published: 2026-02-01
How to capture, decode, and analyze CAN FD bus traffic using Acute protocol analyzers and logic analyzers for automotive electronics development.
CAN FD vs CAN 2.0B: What Changed CAN FD (Flexible Data-rate) extends the classic CAN 2.0B protocol in two important ways. First, it increases the maximum payload from 8 bytes to 64 bytes per frame. Second, it allows the data phase of a frame to transmit at a higher bit rate than the arbitration phase -- typically 2, 5, or 8 Mbit/s for data versus 500 kbit/s for arbitration. The frame format changes are straightforward. CAN FD frames use two new control bits: FDF (FD Format indicator, always recessive) distinguishes FD frames from classic frames, and BRS (Bit Rate Switch) signals the transition to the higher data-phase bit rate. The DLC field is reinterpreted for values above 8 to encode payloads of 12, 16, 20, 24, 32, 48, and 64 bytes. CAN FD retains the same physical layer, arbitration mechanism, and 11-bit or 29-bit identifier structure as CAN 2.0B. This backward compatibility means FD and classic nodes can coexist on the same bus, though classic nodes will flag FD frames as errors and discard them. Why CAN FD Matters for Modern Vehicles Modern vehicles generate far more data than classic CAN can carry. Advanced driver assistance systems (ADAS), over-the-air (OTA) update payloads, diagnostic data, and sensor fusion outputs all demand higher throughput. CAN FD provides a 4-8x throughput improvement without replacing the physical bus infrastructure -- a significant cost advantage over migrating to Automotive Ethernet for every ECU link. Most new vehicle platforms use CAN FD as the primary communication backbone, with CAN 2.0B retained only for legacy ECUs. Debug and validat…

### Stacking Acute Logic Analyzers with Third-Party Oscilloscopes
URL: https://acutena.com/en/learn/dso-stacking-tutorial/
Category: how-to · Published: 2026-01-15
How to combine Acute logic analyzers with your existing oscilloscope for time-correlated analog and digital capture in a single view.
Why Stack a Logic Analyzer with an Oscilloscope Mixed analog and digital debugging is one of the most common scenarios in embedded systems development. You need to see what the firmware is doing on digital buses while simultaneously observing what the hardware is doing on power rails, clock signals, or analog sensor outputs. An oscilloscope alone gives you 2-4 analog channels but no protocol decode. A logic analyzer alone gives you dozens of decoded digital channels but no analog waveforms. Stacking combines both in a single time-correlated view. Typical scenarios where stacking is essential: - SPI communication with power rail droop : An SPI transaction causes a current spike that droops the supply rail, corrupting the transfer. You need to see the SPI decode and the analog voltage droop simultaneously to correlate cause and effect. - Clock jitter during bus activity : An I2C master's clock frequency varies when the CPU is under load. Analog capture of SCL shows the jitter; digital decode shows which transactions are affected. - PWM-controlled power supply debug : A digital PWM signal drives a buck converter. You need to see the digital control signals alongside the analog output voltage ripple and inductor current waveform. - ADC validation : Comparing the analog input signal to the digitized values read out over SPI or I2C confirms ADC linearity and timing. Compatible Oscilloscopes Acute logic analyzers can stack with most oscilloscopes that provide an external trigger output (TRIG OUT) and an external trigger input (EXT TRIG or AUX). This includes instruments from all m…

### eSPI Bus Analysis for Intel Platform Validation
URL: https://acutena.com/en/learn/espi-analysis-guide/
Category: application-note · Published: 2026-01-15
How to capture and analyze eSPI (Enhanced Serial Peripheral Interface) bus traffic for Intel platform bring-up, EC firmware debugging, and system validation.
What Is eSPI and Why It Replaced LPC eSPI (Enhanced Serial Peripheral Interface) is Intel's replacement for the LPC (Low Pin Count) bus that has been used since the late 1990s to connect the chipset to low-speed peripherals like the Embedded Controller (EC), Super I/O, Trusted Platform Module (TPM), and flash storage. Intel introduced eSPI starting with the 6th generation (Skylake) platform and has been phasing out LPC support since. The motivation for the replacement is straightforward. LPC requires 13 signal lines and operates at 33 MHz with a 4-bit data path, yielding a maximum throughput of about 16.67 MB/s. eSPI uses as few as 2 signal lines (clock and a single data line in x1 mode) and scales up to a x4 data path at frequencies up to 66 MHz, providing up to 33 MB/s throughput -- double the LPC bandwidth with fewer pins. The reduced pin count is significant for modern thin-client, laptop, and embedded platforms where PCB routing space is at a premium. eSPI uses a SPI-like physical layer (clock, chip select, and one to four data lines) but adds a channel-based protocol layer on top. This makes eSPI captures look like SPI at the signal level but require eSPI-specific decode to interpret the protocol content. eSPI Channel Architecture eSPI defines four independent logical channels multiplexed over the same physical bus: Peripheral Channel (Channel 0) Handles memory-mapped and I/O-mapped read/write transactions between the host (PCH) and the eSPI slave. This is the primary channel for EC register access, Super I/O configuration, and legacy I/O port emulation. Most EC firmw…

### USB Power Delivery 3.1 Protocol Testing Guide
URL: https://acutena.com/en/learn/usb-pd-testing/
Category: protocol-guide · Published: 2026-01-01
How to capture and analyze USB PD 3.1 negotiations, power contracts, and messaging using Acute protocol analysis instruments.
USB Power Delivery (PD) 3.1 has become the universal standard for negotiated power over USB Type-C connections. With Extended Power Range (EPR) supporting up to 240W (48V / 5A), the protocol now covers everything from smartphone charging to laptop docking stations and even some industrial equipment. Testing PD negotiations correctly is essential for product reliability, safety compliance, and interoperability. USB PD 3.1 Architecture Overview USB PD communication happens over the CC (Configuration Channel) line of the USB Type-C connector. Unlike high-speed USB data which uses differential pairs, PD messaging uses a single-wire half-duplex protocol with Biphase Mark Coding (BMC) at a base rate of 300 kbaud. The PD 3.1 specification defines two power ranges: - Standard Power Range (SPR): Voltages of 5V, 9V, 15V, and 20V with currents up to 5A, maxing out at 100W. This is the range most existing PD devices support. - Extended Power Range (EPR): Adds 28V, 36V, and 48V levels, pushing the ceiling to 240W. EPR requires explicit negotiation and a special Adjustable Voltage Supply (AVS) mode for fine-grained voltage control. A PD transaction consists of structured messages built from a preamble, Start of Packet (SOP), message header, data objects, and a CRC-32. Source Capabilities, Request, Accept, PS RDY, and other message types form the negotiation handshake. CC Line Communication and BMC Encoding BMC encoding represents each bit using transitions within a bit period. A logic 1 produces a mid-bit transition, while a logic 0 has no mid-bit transition, though every bit boundary ha…

### eMMC Interface Analysis with BusFinder
URL: https://acutena.com/en/learn/emmc-analysis/
Category: protocol-guide · Published: 2025-12-15
Deep dive into eMMC protocol analysis using the Acute BusFinder — command decode, data transfer analysis, and performance validation for embedded storage.
Embedded MultiMediaCard (eMMC) is the dominant storage interface in smartphones, tablets, automotive infotainment systems, and countless IoT devices. Unlike removable SD cards, eMMC chips are soldered onto the board, making protocol-level debugging more challenging but also more critical. The Acute BusFinder provides dedicated eMMC protocol decoding that turns raw bus activity into structured command and data transactions. eMMC Architecture Overview An eMMC interface consists of the following signal lines: - CLK: The clock signal driven by the host controller. eMMC supports multiple clock speed modes ranging from 26 MHz (legacy) up to 200 MHz (HS400). - CMD: A bidirectional command/response line. The host sends 48-bit commands, and the device responds with 48-bit or 136-bit responses depending on the command type. - DAT[0:7]: Eight bidirectional data lines for block transfers. Some modes use only DAT[0:3] (4-bit bus width), but most modern eMMC implementations use the full 8-bit bus. - Data Strobe (DS): Used exclusively in HS400 mode. The device drives this signal to provide a read data strobe, enabling the host to sample read data on both edges of the strobe rather than the clock. The protocol follows a command-response model. The host issues commands (CMD0, CMD1, CMD2, etc.), the eMMC device responds, and then data transfers happen on the DAT lines. Commands are grouped into classes: basic commands (class 0), block read (class 2), block write (class 4), erase (class 5), and so on. BusFinder Setup for eMMC Capture Physical Connection The BusFinder connects to eMMC signals…

### Using Streaming Mode for Long-Duration Protocol Monitoring
URL: https://acutena.com/en/learn/streaming-mode-tutorial/
Category: how-to · Published: 2025-12-01
How to use Acute's streaming mode to capture continuous protocol data for hours or days — ideal for intermittent bug hunting and system reliability testing.
Some bugs happen once an hour. Others once a day. Traditional logic analyzer captures use a fixed memory buffer — you arm, trigger, and capture a window of data. That approach works perfectly for reproducible problems, but it completely fails when you are hunting an intermittent fault that might take hours or days to appear. Streaming mode solves this by continuously transferring captured data from the instrument to your PC, using disk storage instead of instrument memory. When Streaming Mode Is Essential Intermittent bus errors: An I2C sensor that NACKs once every few hours, an SPI peripheral that occasionally returns corrupted data, or a UART link that drops characters under specific thermal conditions. These problems cannot be caught with a single-shot capture because you would need to know exactly when to trigger. Long-term reliability testing: Validating that a system operates correctly over extended periods is a requirement for automotive, medical, and industrial applications. Streaming mode lets you record protocol activity for the entire duration of a reliability test and analyze it afterward. Compliance logging: Some standards require continuous logging of bus activity during certification testing. Streaming mode provides an unbroken record of every transaction. Rare event correlation: When a system failure occurs infrequently and involves multiple buses, you can stream multiple protocol channels simultaneously and correlate events across buses after the failure occurs. Setting Up Streaming Capture Hardware Requirements Streaming mode transfers data over the USB co…

### MSO3000: The Most Capable PC-Based Mixed-Signal Instrument
URL: https://acutena.com/en/learn/mso3000-spotlight/
Category: product-spotlight · Published: 2025-11-15
Discover how the MSO3000 combines a 4-channel oscilloscope, 16-channel logic analyzer, and 120+ protocol decoders in one USB 3.0 instrument.
Engineers working on modern embedded systems face a fundamental problem: digital protocols, analog signals, and power rails all interact, and debugging one domain in isolation often misses the real issue. The MSO3000 series was designed to address this by combining a 4-channel digital storage oscilloscope (DSO), a 16-channel logic analyzer (LA), and over 120 protocol decoders in a single USB 3.0 instrument. No switching between tools, no correlating timestamps across separate captures. One instrument, one timebase, one view of your system. Architecture: Analog and Digital in One Box The MSO3000 is a PC-based instrument that connects via USB 3.0 to a Windows computer running Acute's capture and analysis software. It houses two acquisition systems that share a common timebase: Analog subsystem (4 channels): Functions as a full-featured digital storage oscilloscope. Each channel has its own ADC and front-end conditioning. The analog bandwidth, sample rate, and memory depth vary by model (see below), but all models provide simultaneous sampling across all four channels. Digital subsystem (16 channels): A 16-channel logic analyzer with configurable threshold voltages. Each channel can be independently assigned to protocol decoders, bus groups, or used for pattern triggering. The digital channels capture at rates up to the instrument's maximum logic analyzer sample rate. Because both subsystems share the same clock and trigger infrastructure, analog and digital waveforms are inherently time-aligned. You can trigger on a protocol event detected on the digital channels and see the…

### Advanced Protocol Trigger Configuration
URL: https://acutena.com/en/learn/protocol-trigger-configuration/
Category: how-to · Published: 2025-11-01
Master the art of protocol-based triggering on Acute instruments — trigger on specific I2C addresses, SPI commands, UART patterns, and CAN arbitration IDs.
The difference between finding a bug in five minutes versus five hours often comes down to triggering. A basic edge trigger captures everything and leaves you scrolling through thousands of irrelevant transactions. A protocol trigger captures exactly the event you care about, placing it precisely in your acquisition window. Acute instruments support protocol-level triggering across all major serial buses, and learning to configure these triggers effectively is one of the highest-leverage skills for embedded debug. Why Protocol Triggers Matter Consider an I2C bus with eight devices. You are debugging a problem with one specific device at address 0x52. With an edge trigger on SCL, every single I2C transaction from all eight devices fills your capture buffer. You might need to scroll through hundreds of transactions to find the one relevant read from 0x52. With a protocol trigger set to trigger on I2C address 0x52, the instrument ignores all other traffic and captures precisely when your target device is addressed. The same logic applies to every protocol. Protocol triggers reduce the time-to-insight from minutes of scrolling to zero. They are also essential for capturing rare events that would otherwise be lost in a sea of normal traffic. I2C Address Trigger Setup I2C protocol triggering on Acute instruments supports several trigger conditions: Address match: Trigger when a specific 7-bit or 10-bit address appears on the bus. Configure the target address in the trigger setup dialog. You can specify whether to trigger on read, write, or both directions. Address + data match: T…