MSO2116B — Mixed-Signal Logic Analyzer
SKU: MSO2116B
About the MSO2116B
The MSO2116B adds Tier III bus triggers to the 16-channel MSO2000 platform, unlocking eSPI, MIPI I3C, and computing bus analysis. It bridges the gap between simple logic analyzers and full mixed-signal oscilloscopes.
Key Highlights
- Tier I + II + III: adds eSPI, I3C, LPC, MDIO
- 16-channel power sequence validation
- 100+ protocol decoders
- Stack with oscilloscopes for mixed-signal capture
| Digital Channels | 16 |
| Analog Channels | 2 |
| Analog Bandwidth | 40 MHz |
| Timing Analysis | 2 GHz |
| Memory | 4 Gb |
| Power Seq. Channels | 16 |
| Bus Trigger | Tier I + II + III |
| Interface | USB 3.0 |
Support de protocoles
100+ protocoles décodés · 100+ avec déclenchement matériel
103 protocoles pris en charge·DDécodage TDéclenchement EVValidation électrique
| Protocole | Décodage | Déclenchement |
|---|---|---|
| I2C | D | T |
| MIPI I3C | D | T |
| SPI | D | T |
| UART | D | T |
Aucun protocole ne correspond à votre recherche.
Compare Série MSO2000 Models
See how the MSO2116B compares to other models in the Série MSO2000 series.
| Specification | MSO2008E Discontinued | MSO2116E | MSO2116B Current | MSO2216B |
|---|---|---|---|---|
| Digital Channels | 8 | 16 | 16 | 16 |
| Analog Channels | 2 | 2 | 2 | 2 |
| Digital Timing | 2 GHz | 2 GHz | 2 GHz | 2 GHz |
| State Analysis | 200 MHz | 200 MHz | 200 MHz | 200 MHz |
| Analog Bandwidth | 40 MHz | 40 MHz | 40 MHz | 40 MHz |
| Memory | 2 Gb | 4 Gb | 4 Gb | 8 Gb |
| Bus Trigger | Tier I | Tier I, II | Tier I, II, III | Tier I, II, III, IV |
| Protocol Analyzer | Tier I | Tier I, II | Tier I, II, III | Tier I, II, III, IV |
| List Price | — | $1,400 | $3,400 | $3,500 |
Articles connexes
How to Choose the Right Logic Analyzer for Your Project
A practical decision guide for selecting the right Acute logic analyzer or MSO by channel count, sample rate, protocol decode, and portability requirements.
Power Sequence Validation with Acute Logic Analyzers
Learn how to validate multi-rail power-up and power-down sequences on FPGA and SoC designs using Acute logic analyzers with 16-128 channel simultaneous capture.
Complete Guide to I2C Bus Debugging
Practical guide to I2C protocol debugging using Acute instruments — from basic decode setup to advanced trigger configurations for catching elusive bus errors.
Téléchargements
SDK et API
Fiches techniques
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