SWD Protocolos suportados

Sistemas embarcados

Serial Wire Debug

O que é SWD?

SWD (Serial Wire Debug) is a two-pin debug interface defined by ARM as part of the CoreSight debug architecture. SWD provides the same debug functionality as JTAG — register access, memory read/write, breakpoints, and trace — using only two pins: SWDIO (bidirectional data) and SWCLK (clock). SWD is the standard debug interface for ARM Cortex-M, Cortex-A, and Cortex-R processors, making it ubiquitous in microcontroller and embedded processor designs. Engineers analyzing SWD traffic can verify that debug probes are communicating correctly with the target, diagnose firmware download failures, and debug low-level hardware access issues that manifest as SWD read/write errors or WAIT responses from the debug access port.

SWD Referência rápida

type	Serial, synchronous
signals	SWDIO, SWCLK
max Speed	Up to 50 MHz
voltage Range	1.8V – 3.3V
features	ARM debug interface

Instrumentos Acute compatíveis com SWD

Soluções recomendadas

Recomendado para decodificação

TB3016F

Com canais analógicos

MSO2116E

Todos os produtos compatíveis

Decodificação de protocolo

Disparo por hardware

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Como analisar SWD com instrumentos Acute

Conecte seu analisador lógico Acute aos pinos SWDIO e SWCLK no conector de depuração do alvo (tipicamente um conector Cortex Debug de 10 pinos).

Conecte um fio terra a referência de terra da placa alvo.

No software Acute, selecione o SWD protocol decoder e atribua SWDIO e SWCLK aos canais de entrada correspondentes.

Configure o decodificador para expected clock speed and protocol version.

Capture e visualize os SWD transactions showing request packets (APnDP, RnW, address), acknowledgment (OK, WAIT, FAULT), and data phases for debug port register access.

Perguntas frequentes

Qual taxa de amostragem e necessária para a análise SWD ?

SWD clock speeds vary by debug probe — common rates are 1-10 MHz for standard debugging, up to 50 MHz for high-speed trace. Sample at a minimum of 4x the SWCLK frequency. For 10 MHz SWD, use at least 40 MHz sampling. For 50 MHz SWD, sample at 200 MHz or higher. Os analisadores lógicos Acute com análise de temporizado de 2 GHz handle all SWD speeds.

Por que minha sonda de depuração não consegue se conectar ao alvo via SWD?

SWD connection failures are commonly caused by incorrect SWDIO/SWCLK wiring (check pin 2 and pin 4 on the standard 10-pin Cortex Debug connector), missing ground connection, target processor being in a deep sleep state that disables the debug port, or conflicting pin configurations (GPIO function overriding the SWD function on the processor pins). Capture the SWD bus to see if the debug probe is sending the SWD-to-JTAG switching sequence and whether the target is responding with a valid IDCODE.

Quantos canais são necessários para a análise de SWD ?

SWD requires 2 channels: SWDIO and SWCLK. If you also want to capture the nRESET signal (useful for correlating debug access with target resets), add a 3rd channel. For designs that support both SWD and JTAG on the same debug connector, you may want to monitor TDI and TDO as well, bringing the total to 4-5 channels.

Protocolos relacionados

JTAG SPI

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