SWD Protocol Support

Embedded Systems

Serial Wire Debug

What is SWD?

SWD (Serial Wire Debug) is a two-pin debug interface defined by ARM as part of the CoreSight debug architecture. SWD provides the same debug functionality as JTAG — register access, memory read/write, breakpoints, and trace — using only two pins: SWDIO (bidirectional data) and SWCLK (clock). SWD is the standard debug interface for ARM Cortex-M, Cortex-A, and Cortex-R processors, making it ubiquitous in microcontroller and embedded processor designs. Engineers analyzing SWD traffic can verify that debug probes are communicating correctly with the target, diagnose firmware download failures, and debug low-level hardware access issues that manifest as SWD read/write errors or WAIT responses from the debug access port.

SWD Quick Reference

type Serial, synchronous
signals SWDIO, SWCLK
max Speed Up to 50 MHz
voltage Range 1.8V – 3.3V
features ARM debug interface

Acute Instruments Supporting SWD

Recommended Solutions

Recommended for Decode

TB3016F

TB3016F

With Analog Channels

MSO2116E

MSO2116E

All Supporting Products

Protocol Decode
Hardware Trigger
LA4000 Series
LA4000 Series
TravelLogic Series
TravelLogic Series
MSO3000 Series
MSO3000 Series
MSO2000 Series
MSO2000 Series
TravelBus Series
TravelBus Series

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How to Analyze SWD with Acute Instruments

1

Connect your Acute logic analyzer to the SWDIO and SWCLK pins on the target's debug header (typically a 10-pin Cortex Debug connector).

2

Attach a ground lead to the target board's ground reference.

3

In the Acute software, select the SWD protocol decoder and assign SWDIO and SWCLK to the correct input channels.

4

Configure the decoder for the expected clock speed and protocol version.

5

Capture and view decoded SWD transactions showing request packets (APnDP, RnW, address), acknowledgment (OK, WAIT, FAULT), and data phases for debug port register access.

Frequently Asked Questions

What sample rate do I need for SWD analysis?
SWD clock speeds vary by debug probe — common rates are 1-10 MHz for standard debugging, up to 50 MHz for high-speed trace. Sample at a minimum of 4x the SWCLK frequency. For 10 MHz SWD, use at least 40 MHz sampling. For 50 MHz SWD, sample at 200 MHz or higher. Acute logic analyzers with 2 GHz timing analysis handle all SWD speeds.
Why is my debug probe failing to connect to the target over SWD?
SWD connection failures are commonly caused by incorrect SWDIO/SWCLK wiring (check pin 2 and pin 4 on the standard 10-pin Cortex Debug connector), missing ground connection, target processor being in a deep sleep state that disables the debug port, or conflicting pin configurations (GPIO function overriding the SWD function on the processor pins). Capture the SWD bus to see if the debug probe is sending the SWD-to-JTAG switching sequence and whether the target is responding with a valid IDCODE.
How many channels are needed for SWD analysis?
SWD requires 2 channels: SWDIO and SWCLK. If you also want to capture the nRESET signal (useful for correlating debug access with target resets), add a 3rd channel. For designs that support both SWD and JTAG on the same debug connector, you may want to monitor TDI and TDO as well, bringing the total to 4-5 channels.

Related Protocols

JTAG SPI

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