I2S Protocol Support

Audio

Inter-IC Sound

What is I2S?

I2S (Inter-IC Sound) is a synchronous serial bus protocol designed specifically for transmitting digital audio data between integrated circuits. Developed by Philips (now NXP), I2S is the standard interface between audio codecs, DACs, ADCs, DSPs, microcontrollers, and other audio processing components. The protocol uses three signal lines: SCK (Serial Clock, also called BCLK), WS (Word Select, also called LRCLK), and SD (Serial Data). The WS signal indicates whether the left or right audio channel is being transmitted, toggling at the audio sample rate (e.g., 44.1 kHz, 48 kHz, 96 kHz, or 192 kHz). The SCK clock runs at a multiple of the sample rate determined by the bit depth (typically 16, 24, or 32 bits per channel). I2S supports various data formats including standard I2S (data delayed by one BCLK cycle from WS transition), left-justified, and right-justified alignments. The protocol is found in consumer audio products, professional audio equipment, automotive infotainment systems, smart speakers, hearing aids, and any device processing digital audio. Protocol analysis for I2S is important because audio artifacts, channel swaps, clocking errors, and format mismatches between devices are common integration issues. Engineers need to verify that audio data is being transmitted with the correct bit depth, sample rate, and channel alignment to ensure high-quality audio output.

I2S Quick Reference

type Serial, synchronous
signals SCK, WS, SD
max Speed Up to 12.288 MHz
voltage Range 1.8V – 3.3V
bit Depth 16/24/32-bit audio

Acute Instruments Supporting I2S

Recommended Solutions

Recommended for Decode

TB3016F

TB3016F

With Analog Channels

MSO2116E

MSO2116E

With Electrical Validation

MSO3124V

MSO3124V

All Supporting Products

Protocol Decode
Hardware Trigger
Electrical Validation
Protocol Exerciser

TravelBus Series

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How to Analyze I2S with Acute Instruments

1

Connect your Acute logic analyzer to the I2S SCK (BCLK), WS (LRCLK), and SD (data) lines.

2

Attach a ground lead to the target board's ground reference.

3

In the Acute software, select the I2S protocol decoder and assign each signal to the correct channel.

4

Configure the audio format (standard I2S, left-justified, or right-justified), bit depth (16, 24, or 32 bits), and channel configuration.

5

Capture and view decoded audio samples for left and right channels, with sample values displayed in hex or decimal format alongside the timing waveforms.

Frequently Asked Questions

What sample rate do I need for I2S analysis?
The I2S SCK (BCLK) frequency is typically the sample rate multiplied by the number of channels multiplied by bits per sample. For 48 kHz, stereo, 32-bit audio, BCLK is 3.072 MHz. Sample at a minimum of 12 MHz (4x BCLK) for reliable decoding. For high-resolution audio at 192 kHz / 32-bit, BCLK can reach 12.288 MHz, requiring at least 50 MHz sampling.
Why is my I2S decode showing incorrect audio sample values?
Incorrect sample values usually indicate a data format mismatch. I2S standard format delays data by one BCLK cycle after the WS transition, while left-justified and right-justified formats do not. Verify the exact format used by both the transmitter and receiver. Also confirm the bit depth setting — a 24-bit device connected to a 32-bit decoder will produce shifted values.
How many channels are needed for I2S analysis?
Standard I2S requires 3 channels: SCK (BCLK), WS (LRCLK), and SD (data). If your system uses a separate MCLK (master clock) signal, add a fourth channel. For systems with separate I2S data lines for input and output (e.g., codec with ADC and DAC), you need 4-5 channels to capture both data directions simultaneously.

Related Protocols

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