HDLC Protocol Support

Robotics & Industrial

High-Level Data Link Control

What is HDLC?

HDLC (High-Level Data Link Control) is a bit-oriented data link layer protocol defined in ISO 13239, widely used in telecommunications, industrial control, and legacy serial communication systems. HDLC provides a framing mechanism using flag sequences (0x7E), bit-stuffing for transparency, address and control fields, and FCS (Frame Check Sequence) error detection. HDLC is the foundation for many derived protocols including SDLC, LAPB (X.25), LAPD (ISDN), and PPP framing. Engineers debugging telecom interfaces, legacy industrial networks, and point-to-point serial links encounter HDLC framing in many contexts and need protocol analysis to verify frame integrity, identify addressing errors, and diagnose communication failures.

HDLC Quick Reference

type Serial, synchronous/asynchronous
signals DATA, CLK
features ISO 13239 framing protocol

Acute Instruments Supporting HDLC

Recommended Solutions

Recommended for Decode

TB3016F

TB3016F

With Analog Channels

MSO2116E

MSO2116E

All Supporting Products

Protocol Decode
Hardware Trigger
Protocol Exerciser

Supported Product Families

Protocol Decode
Hardware Trigger
LA4000 Series
LA4000 Series
TravelLogic Series
TravelLogic Series
MSO3000 Series
MSO3000 Series
MSO2000 Series
MSO2000 Series
TravelBus Series
TravelBus Series

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How to Analyze HDLC with Acute Instruments

1

Connect your Acute logic analyzer to the HDLC DATA and CLK signals (for synchronous HDLC) or just the DATA signal (for asynchronous framing).

2

Attach a ground lead to the target board's ground reference.

3

In the Acute software, select the HDLC protocol decoder and assign the signals to the correct input channels.

4

Configure the decoder for synchronous or asynchronous mode, address length, and CRC type (CRC-16 or CRC-32).

5

Capture and view decoded HDLC frames showing flag delimiters, address, control field, information payload, and FCS validation status.

Frequently Asked Questions

What sample rate do I need for HDLC analysis?
For synchronous HDLC, sample at a minimum of 4x the clock frequency. Common HDLC clock rates range from 64 kbps (telecom) to several Mbps (industrial), so sample rate requirements vary. For asynchronous HDLC (flag-based framing over UART), use 8-16x the baud rate, same as standard UART analysis.
Why is my HDLC decoder not finding frame boundaries?
HDLC uses the 0x7E flag pattern to delimit frames, with bit-stuffing to prevent the flag pattern from appearing in the data. If the decoder is not finding frames, verify that it is configured for the correct mode (synchronous vs. asynchronous). For synchronous HDLC, ensure the clock signal is properly assigned. Check also that the bit order and any protocol-specific variations (e.g., inverted or scrambled data) are accounted for in the decoder configuration.
How many channels are needed for HDLC analysis?
Synchronous HDLC requires 2 channels: DATA and CLK. Asynchronous HDLC (self-clocking) requires only 1 channel for the data signal. For full-duplex links with separate transmit and receive data lines, add 1 channel per additional data direction. Most HDLC analysis requires 1-3 channels total.

Related Protocols

UART

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