RGMII Protocol Support

Computers & Servers

Reduced Gigabit Media Independent Interface

What is RGMII?

RGMII (Reduced Gigabit Media Independent Interface) is the most widely used MAC-to-PHY interface for Gigabit Ethernet in embedded systems. RGMII achieves 1 Gbps throughput using only 12 signals by employing DDR (Double Data Rate) signaling — data is sampled on both the rising and falling edges of the 125 MHz clock. This makes RGMII timing-critical, as clock-to-data alignment must be maintained within tight margins. RGMII supports 10/100/1000 Mbps operation, with the clock frequency scaling accordingly. Engineers debugging Gigabit Ethernet frequently encounter RGMII timing issues including internal vs. external clock delay configuration, PCB trace length matching, and signal integrity problems at 125 MHz DDR rates.

RGMII Quick Reference

type Parallel, DDR
signals TXD[3:0], RXD[3:0], TX_CLK, RX_CLK, TX_CTL, RX_CTL
max Speed 125 MHz DDR (1 Gbps)
voltage Range 2.5V / 3.3V
standard RGMII v2.0

Acute Instruments Supporting RGMII

Recommended Solutions

Recommended for Decode

TL4234B

TL4234B

All Supporting Products

Protocol Decode
Hardware Trigger
Protocol Exerciser

LA4000 Series

LA4068B
LA4068B
LA4136B
LA4136B

MSO2000 Series

MSO2216B
MSO2216B

MSO3000 Series

MSO3124H
MSO3124H
MSO3124V
MSO3124V

TravelLogic Series

TL4234B
TL4234B

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How to Analyze RGMII with Acute Instruments

1

Connect your Acute logic analyzer to the RGMII signals: TXD[3:0], TX_CLK, TX_CTL, RXD[3:0], RX_CLK, and RX_CTL.

2

Attach a ground lead to the target board's ground reference.

3

In the Acute software, select the RGMII protocol decoder and assign each signal to the correct input channel.

4

Configure the decoder for the expected speed mode (1 Gbps DDR, 100 Mbps, or 10 Mbps).

5

Capture and view decoded Ethernet frames, and use timing analysis to verify clock-to-data alignment on both clock edges.

Frequently Asked Questions

What sample rate do I need for RGMII analysis?
RGMII at 1 Gbps uses a 125 MHz clock with DDR data, meaning data transitions occur at 250 MHz effective rate. Sample at a minimum of 500 MHz for basic frame decoding. For timing analysis of clock-to-data skew and setup/hold margins, a sample rate of 1 GHz or higher is recommended. Acute logic analyzers with 2 GHz timing analysis are well-suited for RGMII timing validation.
Why does my RGMII link work at 100 Mbps but fail at 1 Gbps?
This is almost always a clock delay configuration issue. RGMII at 1 Gbps requires a 2 ns (90-degree) clock delay to properly center the clock within the data eye. At 100 Mbps, timing margins are much more forgiving so the link works without precise delay. Check whether the PHY is configured for internal clock delay (RGMII-ID mode) or if the PCB provides external delay through trace length. Capture the RGMII signals and measure the actual clock-to-data timing relationship.
How many channels are needed for RGMII analysis?
Full bidirectional RGMII analysis requires 12 channels: TXD[3:0], TX_CLK, TX_CTL (6 TX), RXD[3:0], RX_CLK, RX_CTL (6 RX). For unidirectional monitoring, 6 channels cover one direction. Adding MDIO management bus signals (MDC, MDIO) brings the total to 14 channels. The LA4000 series provides adequate channel count for full RGMII analysis.

Related Protocols

MII GMII

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